The invention relates generally to clock circuits and more specifically to circuits for interfacing subsystems having different timing characteristics and tolerances.
In communications systems, such as those for broadcasting, teleconferencing, computer networking, etc., various kinds of modulation techniques are used. Use of these modulation techniques typically requires the availability of precise and accurate modulation frequencies. With the advances of integrated circuit technology, it is increasingly popular for communication systems to apply digital techniques for data/signal processing and data transmission. Therefore, the ability to generate accurate frequencies in synchronous digital systems is essential.
Different modulation standards stipulate greatly different accuracies for modulation frequencies. For example, in telecommunication systems, the frequency of system clocks is typically constrained by international organizations such as CCITT to have errors of no more than 0.01 percent, whereas system clocks of, for example, graphics systems for Personal Computers (PCs) may be in error by as much as 0.25 percent without violating relevant specifications.
With regard to terminology, an "accurate" clock is one that possesses a specified, nominal frequency, and a "stable" clock is one that does not vary in frequency over time, for example, despite temperature fluctuations in a circuit. The terms "accurate" and "stable" will sometimes be used in a relative sense to mean "more nearly accurate" and "more nearly stable," respectively.
There are applications in which a synchronous system with inaccurate clock frequency needs to communicate to another system that requires a predefined accurate and stable signal frequency. An example of such an application is the display of computer graphics onto standard television sets. As mentioned above, in a PC graphics system, the system clock need not be very accurate (system clocks can be off by as much as 0.25 percent). In contrast, a standard television set typically expects a subcarrier frequency that is accurate and stable to better than 100 parts per million (i.e., 0.01 percent). Hence, it is desirable to have a technique that can generate an accurate and stable signal frequency in a system with an inaccurate system clock frequency while maintaining system synchronization. In particular, it is desirable that the generated signal be synchronous with the system clock.
It is apparent that it would be impractical to try to derive any accurate signal frequency directly from an inaccurate system clock. However, if an accurate and stable reference frequency is available, then techniques and systems exist which can derive an accurate and stable frequency based on the reference clock while remaining synchronous with the inaccurate system clock. One such system is found in the "Chrontel CH7001 VGA to NTSC/PAL Encoder" integrated circuit product (CH7001), Chrontel, Inc., San Jose, Calif.
FIG. 1 illustrates at a high level the clock generator of prior art systems similar to the system in the Chrontel CH7001 product. The clock generator includes a clock measuring circuit 10 that produces a system clock measurement Nr 15. The system clock measurement Nr 15 is a digital value, and is provided to a P:Q ratio counter 20 that generates, in response to Nr 15 and a system clock 25, an output clock signal 30 of output frequency Fo. The output frequency Fo is related to the system clock frequency Fs by the equation: EQU Fo=P/Q*Fs (1)
wherein Q is a constant parameter of the P:Q ratio counter 20 and: EQU P=Nr (2)
As Equation 1 shows, the P:Q ratio counter produces an output clock whose frequency Fo is a function of the system clock frequency Fs and the parameter P, where P is the system clock measurement Nr. The P:Q ratio counter is explained in more detail below in the detailed Description of Specific embodiments.
The clock measuring circuit 10 includes a system counter 35, which receives the system clock signal 25 and counts a predetermined number Ns 40 of transitions therein to delimit a test time period using a timing signal 45. A reference counter 50 receives and counts transitions in an accurate, stable reference clock signal 55 (typically, a crystal-based clock signal) of frequency Fr during the test time period. At the end of the test time period, the output 60 of the reference counter 55 is latched into a buffer 65 to be provided as the system clock measurement Nr 15 to the P:Q ratio counter 20. A controller 70 is coupled to control operation of the system counter 35, the reference counter 50, and the buffer 65. The controller 70 may be coupled (not shown) to receive the system clock signal 25 or the reference clock signal 55, depending on its design.
The relationship between Ns, Nr, Fs, and Fr of the clock measuring circuit 10 is given by: EQU Nr=Ns*Fr/Fs (3)
which represents the test time period, Ns*(1/Fs), multiplied by Fr, the number of reference clock periods per second. Combining Equations 1, 2, and 3 gives: ##EQU1## Equation 4 shows that, since Ns, Q, and Fr are well-defined, accurate and stable values, an accurate and stable Fo is generated. Furthermore, a desired Fo can be realized simply by choosing appropriate values of Ns and Q, given Fr. Note that typically, Fr &gt;Fo. Note also that the value of Ns may be switched during operation to cause a new output frequency Fo to be produced by the system, even though the system has but a single reference clock frequency Fr.
Most importantly, the output clock frequency Fo can be realized regardless of the system clock frequency Fs. If the system clock signal is inaccurate but stable, then the system works well. Even if the system clock frequency Fs slowly drifts over time, the clock measuring circuit 10 will update the system clock measurement 15 to maintain a generally correct output frequency Fo (provided that the drift is slow in relation to the test time period).
It is important to note that the system clock measurement Nr 15 should change only in response to actual drifts in the system frequency Fs or to a change in the value of system parameter Ns. Fluctuation in the value of Nr caused by any other reason translates into an undesired shift in the value of the output frequency Fo, and therefore constitutes a type of instability in the output clock signal 30. For example, if within a stream of successive test time periods, the system clock measurement Nr were to fluctuate for one test time period, then, referring to FIG. 2, the actual output clock frequency 200 would also fluctuate by an amount .DELTA.Fo 210 for one test time period 220 from the steady, nominal frequency Fo(nom) 230. In consequence, if Fo is used as the modulation signal frequency of a communication system, a fluctuating output clock frequency Fo would be interpreted as "noise" in the receiver.
Unfortunately, Fs and Fr are not synchronous, and there will be some finite but small errors between the counts of the system counter 35 and the reference counter 50. The result of this error will introduce a fluctuation in Nr.